1. Field of the Invention
The present invention relates generally to a recess channel transistor, and more particularly to a recess channel transistor and a method of forming the same, which can prevent deterioration of transistor characteristics due to misalignment between a recess gate and a top gate on the recess gate.
2. Description of the Prior Art
Recently, as the design rule for currently developing semiconductor memory devices reduces the device sizes below sub-100 nm, it has become very difficult to secure sufficient data retention time. When the minimum feature size is reduced, doping density in a substrate must be increased. Thus, if the doping density in the substrate becomes higher, the electric field and the junction leakage must also increase. Therefore, in order to realize a target threshold voltage Vt required by a certain semiconductor memory device, a transistor having an existing planar structure faces a limitation in view of processing and device characteristics.
Accordingly, a recess channel transistor structure extending the channel length has been proposed as a method for decreasing the substrate doping density. Such a recess channel transistor can reduce the substrate doping density, thereby extending the data retention time. Further, such a recess channel transistor can lower the electric field, thereby making it possible to obtain an excellent refreshing characteristic. In addition, as the channel length increases, it is possible to improve characteristics of DIBL and BVds, resulting in the improvement of cell characteristics.
Hereinafter, a conventional method for forming a recess channel transistor, which had been previously proposed, will be described in brief.
First, a recess mask is formed on a semiconductor substrate to expose an activation region in which gates are formed. Then, the exposed activation region of the substrate is etched so as to form recesses. Next, after the recess mask is removed, a gate insulation layer is formed on a bottom surface of each recess. Sequentially, after a gate conductive layer is formed on a whole surface of the substrate in order to fill in the recesses, a hard mask layer is formed on the gate conductive layer.
In turn, the hard mask layer and the gate conductive layer are etched so as to form a gate in each recess. Next, after a Lightly Doped Drain (LDD) ion implant process is performed on the resultant of the substrate, a spacer is formed at both side walls of each gate. Then, source/drain regions are formed at both sides of each gate, including the spacer on the surface of the substrate, thereby establishing the formation of the recess channel transistor.
In the recess channel transistor formed by the method described above, it is important that the two transistors which are formed in a cell have the same shapes. Thus, the gate formed in the recess must be accurately aligned with the top gate integrated with the recess gate.
However, it is substantially difficult to control the alignment of the recess gate with the top gate. Thus, the misalignment of the recess gate with the top gate may occur. It causes a change in the characteristics of the transistor, which thereby fails to obtain desired cell characteristics.
FIG. 1 is a cross-sectional view for illustrating a conventional recess channel transistor. Problems in the conventional transistor will be described in brief.
As shown in FIG. 1, various factors relating to the processes cause the misalignment of the recess gate 104a with the top gate 104b to be integrated with the recess gate. In this case, in view of a storage node, a left transistor differs structurally from a right transistor. This causes both transistors to have different threshold voltage Vt. Thus, the difference in the threshold voltage Vt between both transistors causes a tWR characteristic to be weak when a cell has a relatively high threshold voltage, while causing an Ioff characteristic to be weak when the cell has a relatively low threshold voltage. As a result, it is difficult to store data in the cell.
Further, the misalignment of the recess gate 104a with the top gate 104b causes the recess gate 104a to be subjected to etching damages. Thus, the gate insulation layer 103 at the channel becomes thick, thereby abnormally increasing the threshold voltage so that tREF/tWR characteristics deteriorate.
In FIG. 1, a reference numeral “101” denotes a semiconductor substrate, a reference numeral “102” indicates a device insulation layer, and a reference numeral “105” denotes a hard mask layer. Further, reference numerals “106”, “107”, and “108” respectively indicate a spacer, a source region in contact with a storage nod, and a drain region in contact with a bit line.